The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a semiconductor device which has power-MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) type structure and to its manufacturing method.
The conventional power metal-oxide semiconductor field effect transistor is manufactured, for example, by forming an n-type epitaxial-growth layer on an n+-type substrate of high concentration and by forming MOSFET structure on the surface thereof. In this structure, a high breakdown voltage can be realized by extending a depletion layer in the n-type epitaxial-growth layer. However, since a resistance of the n-type epitaxial-growth layer for realizing a high breakdown voltage is high, the resistance of the element (called Ron: “ON resistance” etc.) in an ON state will become high.
Then, in order to improve this trade-off relation, the MOSFET in which p-n stripe and pillar structure are provided has been proposed. In these MOSFETs, the MOSFET is formed in the upper part of the p-n stripe or the p-type pillar. The Ron can be lowered by making the n-type layers of comparatively high-concentration as current paths, and the breakdown voltage can be raised by making the p-n pillar into perfect depletion.
However, in the case of such structures, the pillar structure has been fabricated by repeating ion implantation and epitaxial growth, and has been formed by performing prolonged activation processing at high temperature to the last. For this reason, accuracy of the alignment was limited between the process of the ion implantation and the process of the epitaxial growth, and the pillar was expanded by activation processing. Therefore, it was difficult to form the pillar with high density.